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INTEGRATED CIRCUITS
PCA9510; PCA9511 Hot swappable I2C and SMBus bus buffer
Product data sheet Supersedes data of 2003 Dec 18 2004 Oct 05
Philips Semiconductors
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
DESCRIPTION
The PCA9510 and PCA9511 are hot swappable I2C and SMBus buffers that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510 and PCA9511 provides bi-directional buffering, keeping the backplane and card capacitances isolated. The PCA9511 rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements, while the PCA9510 has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510 and PCA9511 incorporate a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9510 (IN only) and PCA9511 SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers allow them to be connected to another PCA9510/11/12/13/14 device in series or in parallel and to the A side of the PCA9517. The PCA9510/11/12/13/14 can not connect to the static offset I/Os used on the PCA9515/15A/16/16A/17 B side and PCA9518.
FEATURES
* Bi-directional buffer for SDA and SCL lines increases fanout and
prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems
* Compatible with I2C standard mode, I2C fast mode, and SMBus
standards
* V/t rise time accelerators on all SDA and SCL lines (PCA9511
only)
* Rise time accelerator threshold of 0.6 V * Active high ENABLE input * Active high READY open-drain output * High impedance SDA and SCL pins for VCC = 0 V * 1 V precharge on all SDA and SCL lines (PCA9510 IN only) * Supports clock stretching and multiple master
arbitration/synchronization
APPLICATION
* cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an operating system.
* Operating power supply voltage range: 2.7 V to 5.5 V * 5.5 V tolerant I/Os * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
* Latch-up testing is done to JEDEC Standard JESD78 which * Package offer: SO8, TSSOP8 (MSOP8)
ORDERING INFORMATION
PACKAGES 8-pin plastic SO 8-pin plastic SO 8-pin plastic TSSOP (MSOP) 8-pin plastic TSSOP (MSOP) TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C ORDER CODE PCA9510D PCA9511D PCA9510DP PCA9511DP TOPSIDE MARK PCA9510 PCA9511 9510 9511 DRAWING NUMBER SOT96-1 SOT96-1 SOT505-1 SOT505-1 exceeds 100 mA
Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
2004 Oct 05
2
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
PIN CONFIGURATION
TOP VIEW ENABLE 1 SCLOUT SCLIN GND 2 3 4 8 7 6 5 VCC SDAOUT SDAIN READY
PIN DESCRIPTION
PIN 1 SYMBOL ENABLE DESCRIPTION Chip enable pin. Grounding this pin puts the part in a low current (<1 A) mode. It also disables the rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Serial clock output to and from the SCL bus on the card. Serial clock input to and from the SCL bus on the backplane. Ground. Connect this pin to a ground plane for best results. This is an open-drain output which pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT and SCLOUT, and turns off when the two sides are connected. Serial data input to and from the SDA bus on the backplane. Serial data output to and from the SDA bus on the card. Power supply.
2 3
SCLOUT SCLIN GND READY
SW01045
Figure 1. Pin configuration. 4 5
6 7 8
SDAIN SDAOUT VCC
FEATURE SELECTION CHART
FEATURES Idle detect High impedance SDA, SCL pins for VCC = 0 V Rise time accelerator circuitry on all SDA and SCL lines Rise time accelerator circuitry hardware disable pin for lightly loaded systems Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin Ready open drain output Two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDA and SCL lines 92 A current source on SCLIN and SDAIN for PICMG applications PCA9510 Yes Yes -- -- -- Yes -- IN only -- PCA9511 Yes Yes Yes -- -- Yes -- Yes -- PCA9512 Yes Yes Yes Yes -- -- Yes Yes -- PCA9513 Yes Yes Yes -- Yes Yes -- -- Yes PCA9514 Yes Yes Yes -- Yes Yes -- -- --
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
TYPICAL APPLICATION -- PCA9510
VCC (2.7 V to 5.5 V) R1 10 k R2 10 k 3 8
C1 0.01 F
R5 10 k 2
R3 10 k
R4 10 k
SCLIN
SCLOUT
SDAIN
6
7
SDAOUT
ENABLE
1 ENABLE GND 4 READY
5
SW02149
Figure 2. Typical application -- PCA9510
BLOCK DIAGRAM -- PCA9510
8 SDAIN 6 CONNECT BACKPLANE-TO-CARD CONNECTION CONNECT ENABLE 100 k RCH1 1 VOLT PRECHARGE 100 k RCH2 CONNECT 7
VCC SDAOUT
SCLIN 3 CONNECT
BACKPLANE-TO-CARD CONNECTION CONNECT
2
SCLOUT
0.55VCC/ 0.45VCC
0.5 A 0.55VCC/ 0.45VCC UVLO ENABLE 1 130 s DELAY
STOP BIT AND BUS IDLE
20 pF UVLO RD QB S
CONNECT
5
READY
4
GND
CONNECT 0.5 pF
SW02150
Figure 3. Block diagram -- PCA9510
2004 Oct 05
4
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
TYPICAL APPLICATION -- PCA9511
VCC (2.7 V to 5.5 V) R1 10 k R2 10 k 3 8
C1 0.01 F
R5 10 k 2
R3 10 k
R4 10 k
SCLIN
SCLOUT
SDAIN
6
7
SDAOUT
ENABLE
1 ENABLE GND 4 READY
5
SW02151
Figure 4. Typical application -- PCA9511
BLOCK DIAGRAM -- PCA9511
2 mA SLEW RATE DETECTOR SDAIN 6 CONNECT BACKPLANE-TO-CARD CONNECTION CONNECT ENABLE 100 k RCH1 1 VOLT PRECHARGE 100 k RCH2 2 mA SLEW RATE DETECTOR SCLIN 3 CONNECT BACKPLANE-TO-CARD CONNECTION CONNECT 0.55VCC/ 0.45VCC 2 mA SLEW RATE DETECTOR 2 100 k RCH4 100 k RCH3 CONNECT 2 mA SLEW RATE DETECTOR
8 7
VCC SDAOUT
SCLOUT
0.5 A 0.55VCC/ 0.45VCC UVLO ENABLE 1 130 s DELAY
STOP BIT AND BUS IDLE
20 pF UVLO RD QB S
CONNECT
5
READY
4
GND
CONNECT 0.5 pF
SW01051
Figure 5. Block diagram -- PCA9511 2004 Oct 05 5
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
OPERATION Start-up
An under voltage/initialization circuit holds the parts in a disconnected state which presents high impedance to all SDA and SCL pins during power-up. A low on the enable pin also forces the parts into the low current disconnected state when the ICC is essentially zero. As the power supply is brought up and the enable is high or the part is powered and the enable is taken from low to high it enters an initialization state where the internal references are stabilized and the precharge circuit for PCA9510 (IN only) and PCA9511 are enabled. At the end of the initialization state the "Stop Bit And Bus Idle" detect circuit is enabled. With the enable pin high long enough to complete the initialization state and remaining high when all the SDA and SCl pins have been high for the bus idle time or when all pins are high and a stop condition is seen on the SDAIN and SCLIN pins, SDAIN is connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry is activated during the initialization and is deactivated when the connection is made. The precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 k nominal resistors. This precharges the pins to 1 V to minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels.
Maximum number of devices in series
Each buffer adds about 0.065 V dynamic level offset at 25 C with the offset larger at higher temperatures. Maximum offset (VOS) is 0.150 V. The LOW level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if lightly loaded the VOL may be 0.1 V. Assuming VOL = 0.1 V and VOS = 0.1 V, the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the rising edge accelerator (about 0.6 V). With great care a system with four buffers may work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two. The PCA9510 (rise time accelerator is permanently disabled) and the PCA9512 (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. If the VIL is above 0.6 V and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected; so if the noise is small enough it may be possible to use more than two PCA9510 or PCA9512 parts in series but is not recommended.
Connect Circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. A low forced on either SDAIN or SDAOUT will cause the other pin to be driven to a low by the part. The same is also true for the SCL pins. Noise between 0.7VCC and VCC is generally ignored because a falling edge is only recognized when it falls below 0.7VCC with a slew rate of at least 1.25 V/s. When a falling edge is seen on one pin the other pin in the pair turns on a pull down driver that is referenced to a small voltage above the falling pin. The driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the first falling pin is below 0.7VCC. The first falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate then the initial pull down rate will continue. If the first falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage the they will both continue down at the slew rate of the first. Once both sides are low they will remain low until all the external drivers have stopped driving lows. If both sides are being driven low to the same value for instance, 10 mV by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. This bounce is worst for low capacitances and low resistances, and may become excessive. When the last external driver stops driving a low, that pin will bounce up and settle out out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25 V/s, when the pin voltage exceeds 0.6 V for the PCA9511, the rise time accelerators circuits are turned on and the pull down driver is turned off.
buffer A MASTER common node buffer C SLAVE C buffer B SLAVE B
SW02353
Figure 6. Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of Buffer A and Buffer B in series as shown in Figure 6. Consider if the VOL at the input of Buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change you would observe VIL at the input of Buffer A of 0.3 V and its output, the common node, is 0.4 V. The output of Buffer B and Buffer C would be 0.5 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of Buffer C is 0.5 V. When the Master pull-down turns off, the input of Buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node will rise to 0.5 V before Buffer B's output turns on, if the pull-up is strong the node will bounce. If the bounce goes above the threshold for the rising edge accelerator 0.6 V the accelerators on both Buffer A and Buffer C will fire contending with the output of Buffer B. The node on the input of Buffer A will go HIGH as will the input node of Buffer C. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to 0.5 V because the Buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to 0.6 V until Slave B turned off. This would not cause a failure on the data line as long as the return to 0.5 V on the common node (0.6 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on Buffer A and Buffer C would see a false clock rather than a stretched clock, which would cause a system error.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
Propagation Delays
The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The tPHL can never be negative because the output does not start to fall until the input is below 0.7VCC, and the output turn on has a non zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL occurs when the input is driven low with zero delay and the output is still limited by its turn on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature. VCC and process, as well as the load current and the load capacitance.
RPULLUP (k)
30
25 RMAX = 24 k 20
15 RISE-TIME > 300 ns
21 RECOMMENDED PULL-UP 5
0 0 100 CBUS (pF) 200 300 400
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on to quickly slew the SDA and SCL lines high once the input level of 0.6 V for the PCA9511 is exceeded. The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators. The PCA9510 doesn't have any rise time accelerator circuitry.
SW02115
Figure 7. Bus requirements for 3.3 V systems
20 RPULLUP (k) 15 RMAX = 16 k RISE-TIME > 300 ns 21 RECOMMENDED PULL-UP 5
READY Digital Output
This pin provides a digital flag which is low when either ENABLE is low or the start-up sequence described earlier in this section has not been completed. READY goes high when ENABLE is high and start-up is complete. The pin is driven by an open drain pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of 10 k to VCC to provide the pull-up.
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives READY low, disables the bus precharge circuitry, and puts the part in a low current state. When the pin voltage is driven all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides.
0 0 100 200 CBUS (pF) 300 400
Resistor Pull-up Value Selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/s on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula: R v 800 @ 10 3 V CC(MIN) * 0.6 C
SW02116
Figure 8. Bus requirements for 5 V systems
Minimum SDA and SCL Capacitance Requirements
The device connection circuitry requires a minimum capacitance loading on the SDA and SCL pins in order to function properly. The value of this capacitance is a function of VCC and the bus pull-up resistance. Estimate the bus capacitance on both the backplane and the card data and clock buses, and refer to Figures 7 and 8 to choose appropriate pull-up resistor values. Note from the figures that 5 V systems should have at least 47 pF capacitance on their buses and 3.3 V systems should have at least 22 pF capacitance for proper operation. Although the device has been designed to be marginally stable with smaller capacitance loads, for applications with less capacitance, provisions need to be made to add a capacitor to ground to ensure these minimum capacitance conditions if oscillations are noticed during initial signal integrity verification.
where R is the pull-up resistor value in , VCC(MIN) is the minimum VCC voltage in volts and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R 16 k for VCC = 5.5 V maximum, R 24 k for VCC = 3.6 V maximum. The start-up circuitry requires logic high voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figures 7 and 8 for guidance in resistor pull-up selection.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
Hot Swapping and Capacitance Buffering Application
Figures 9 through 11 illustrate the usage of the PCA9510 and PCA9511 in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to
meet. Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9510 and PCA9511 drive the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, Hot Swap Bus Buffer for more information on applications and technical assistance.
BACKPLANE CONNECTOR BACKPLANE STAGGERED CONNECTOR VCC R1 10 k BD_SEL SDA SCL R2 10 k I/O PERIPHERAL CARD 1 POWER SUPPLY HOT SWAP R3 10 k VCC C1 0.01 F R4 10 k R5 10 k R6 10 k CARD1_SDA CARD1_SCL
ENABLE SDAIN SCLIN
SDAOUT SCLOUT
GND
READY
I/O PERIPHERAL CARD 2 POWER SUPPLY HOT SWAP STAGGERED CONNECTOR R7 10 k C3 0.01 F R8 10 k R9 10 k R10 10 k CARD2_SDA CARD2_SCL
ENABLE SDAIN SCLIN
VCC
SDAOUT SCLOUT
GND
READY
I/O PERIPHERAL CARD N POWER SUPPLY HOT SWAP STAGGERED CONNECTOR R11 10 k VCC C5 0.01 F R12 10 k R13 10 k R14 10 k CARDN_SDA CARDN_SCL
ENABLE SDAIN SCLIN
SDAOUT SCLOUT
GND
READY
SW02126
NOTE: The PCA9510 and PCA9511 can be used in any combination depending on the number of rise time accelerators that are needed by the system. Normally only one PCA9511 would be required per bus. Figure 9. Hot swapping multiple I/O cards into a backplane using the PCA9510 and PCA9511 in a CompactPCI, VME, and AdvancedTCA system
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
BACKPLANE CONNECTOR BACKPLANE STAGGERED CONNECTOR VCC R1 10 k R2 10 k I/O PERIPHERAL CARD 1
C1 0.01 F
R4 10 k
R5 10 k
R6 10 k CARD_SDA CARD_SCL
ENABLE SDAIN SCLIN
VCC
SDAOUT SCLOUT
SDA SCL
GND C2 0.01 F
ACC
I/O PERIPHERAL CARD 2
STAGGERED CONNECTOR
C3 0.01 F
R8 10 k
R9 10 k
R10 10 k CARD2_SDA CARD2_SCL
ENABLE SDAIN SCLIN
VCC
SDAOUT SCLOUT
GND C4 0.01 F
ACC
SW02121
Figure 10. Hot swapping multiple I/O cards into a backplane using the PCA9510 and PCA9511 in a PCI system
RDROP VCC R1 10 k R4 10 k
VCC_LOW C2 0.01 F R2 1 k R3 1 k R5 10 k
VCC ENABLE SDA SCL SDAIN SCLIN GND SDAOUT SCLOUT READY SDA2 SCL2
SW02123
Figure 11. System with disparate VCC voltages
2004 Oct 05
9
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134). Voltages with respect to pin GND. LIMITS SYMBOL VCC Vn II IIO Topr Tstg Tsld Tj(max) Supply voltage range VCC SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE Maximum current for inputs Maximum current for I/O pins Operating temperature range Storage temperature range Lead soldering temperature (10 sec max) Maximum junction temperature PARAMETER MIN. -0.5 -0.5 - - -40 -65 - - MAX. +7 +7 20 50 +85 +125 +300 +125 UNIT V V mA mA C C C C
NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
ELECTRICAL CHARACTERISTICS
SYMBOL Power supply VCC ICC ICC(sd) Supply voltage Supply current PARAMETER
VCC = 2.7 V to 5.5 V; Tamb = -40 to +85 C unless otherwise noted. TEST CONDITIONS LIMITS MIN. 2.7 -- -- TYP. -- 2.8 200 MAX. 5.5 6 -- UNIT
Note 1. VCC = 5.5 V; VSDAIN = VSCLIN = 0 V; Note 1. VENABLE = 0 V, all other pins at VCC or GND SDA, SCL floating; Note 1.
V mA A
Supply current in shut-down mode
Start-up circuitry VPRE VEN VDIS IEN tEN tIDLE tDIS tSTOP tREADY IOFF Ci CO VOL(READY) Precharge voltage Enable threshold voltage Disable threshold voltage Enable input current Enable delay or initialization time Bus idle time Disable time, ENABLE to Ready SDAIN to READY deLay after STOP SCLOUT/SDAOUT to READY Ready off state leakage current ENABLE capacitance Ready capacitance LOW-level output voltage on READY pin Transient boosted pull-up current Note 7 Note 7 VEN = VCC VI = VCC or GND, Note 4 VI = VCC or GND, Note 4 Ipull-up = 3 mA; VEN = VCC; Note 1. Note 1. Enable from 0 V to VCC 0.8 -- 0.3 x VCC -- -- 50 -- -- -- -- -- -- -- 1.0 0.5 x VCC 0.5 x VCC 0.1 130 120 15 1.3 1.2 0.3 2 2 -- 1.2 0.7 x VCC -- 1 -- 250 -- -- -- -- -- -- 0.4 V V V A s s ns s s A pF pF V
Rise time accelerators IPULLUPAC Positive transition on SDA, SCL, VCC = 2.7 V; Slew rate = 1.25 V/s Note 2. 1 2 -- mA
Input-output connection VOS fSCL_SDA tPLH tPHL CIN VOL Input-output offset voltage operating frequency SCL to SCL and SDA to SDA SCL to SCL and SDA to SDA Digital input capacitance LOW-level output voltage 10 k to VCC, CL = 100 pF each side 10 k to VCC, CL = 100 pF each side Note 4 Input = 0 V, SDA, SCL pins, ISINK = 3 mA; VCC = 2.7 V; Note 1 SDA, SCL pins = VCC = 5.5 V 10 k to VCC on SDA, SCL; VCC = 3.3 V; Note 1; Note 3. 0 0 -- -- -- 0 65 -- 25 380 -- -- 150 400 -- -- 10 0.4 mV kHz ns ns pF V
ILI
Input leakage current
--
--
5
A
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
SYMBOL System characteristics fI2C tBUF thD,STA tsu,STA tsu,STO thD,DAT tsu,DAT tLOW tHIGH tt tr
PARAMETER
TEST CONDITIONS
LIMITS MIN. TYP. MAX.
UNIT
I2C operating frequency Bus free time between stop and start condition Hold time after (repeated) start condition Repeated start condition setup time Stop condition setup time Data hold time Data setup time Clock low period Clock high period Clock, data fall time Clock, data rise time Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Notes 4 and 5 Notes 4 and 5
0 1.3 0.6 0.6 0.6 300 100 1.3 0.6 20 +0.1 x CB 20 +0.1 x CB
-- -- -- -- -- -- -- -- -- -- --
400 -- -- -- -- -- -- -- -- 300 300
kHz s s s s ns ns s s ns ns
NOTES: 1. This specification applies over the full operating temperature range. 2. IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. 3. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in the Typical Performance Characteristics section. 4. Guaranteed by design, not production tested. 5. CB = total capacitance of one bus line in pF. 6. SDA_IN/SCL_IN = 0.1 V, SDA_OUT/SCL_OUT through resistor to VCC. 7. Delays that can occur after ENABLE and/or idle times have passed.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
TYPICAL PERFORMANCE CHARACTERISTICS
2.5 2.4 VCC = 5.5 V 2.3 2.2 I CC (mA) 2.1 2.0 1.9 350 1.8 1.7 -40 +25 TEMPERATURE (C) +85 325 -40 +25 TEMPERATURE (C) +85 CIN = COUT = 100 pF RPULLUPIN = RPULLUPOUT = 10 k 400 (ns) VCC = 3.3 V 375 VCC = 5.5 V
PHL
450
425
VCC = 2.7 V
VCC = 3.3 V VCC = 2.7 V
t
SW02152
SW02153
Figure 12. ICC versus Temperature.
12
Figure 14. Input-output tPHL versus Temperature.
100
10
VCC = 5 V
90
I PULLUPAC (mA)
VOUT - VIN (mV)
8
80 VCC = 3.3 V OR 5.5 V 70
6 VCC = 3.0 V
4
60
2 VCC = 2.7 V 0 -40 +25 TEMPERATURE (C) +85
50
40 0 10,000 20,000 RPULLUP () 30,000 40,000
SW01049
SW02154
Figure 13. IPULLUPAC versus Temperature.
Figure 15. Connection circuitry VOUT - VIN.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
SDAx/SCLx
ENABLE
READY
tEN
tIDLE tDIS
SW02155
Figure 16. Timing for tENABLE, tIDLE, and tDISABLE
SDAIN
SCLIN SCLOUT SDAOUT
ENABLE
READY
tEN tSTOP
SW02156
Figure 17. tSTOP that can occur after tENALBE
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Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
SCLIN/SDAIN SCLOUT/SDAOUT
ENABLE
tEN tIDLE
READY
tREADY
SW02157
Figure 18. tREADY delay that can occur after tENALBE and tIDLE
VCC
VCC
RL = 10 k VI PULSE GENERATOR RT D.U.T. CL= 100 pF VO
DEFINITIONS
RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators.
SW02345
Figure 19. Test circuitry for switching times
2004 Oct 05
15
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2004 Oct 05
16
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
2004 Oct 05
17
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
REVISION HISTORY
Rev _2 Date 20041005 Description Product data sheet (9397 750 13998). Supersedes data of 2003 Dec 18 (9397 750 12561). Modifications:
* "Description" section on page 2: add fourth paragraph. * "Features" section on page 2, last bullet: add "(MSOP8)" * Add section "Maximum number of devices in series" on page 6. * Section "Minimum SDA and SCL Capacitance Requirements" on page 7 re-written * Delete (old) Figure 10 "Repeater/bus extender application using the PCA9510 and PCA9511" * `Absolute Maximum Ratings' table on page 10: add parameters II and IIO. * Electrical characteristics, subsection "System characteristics" on page 12: change Unit for thd;DAT and tsu;DAT
from s to ns.
* Figure 19 modified.
_1 20031218 Product data (9397 750 12561). ECN 853-2442 01-A14987 dated 15 December 2003.
2004 Oct 05
18
Philips Semiconductors
Product data sheet
Hot swappable I2C and SMBus bus buffer
PCA9510; PCA9511
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 10-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 13998
Philips Semiconductors
2004 Oct 05 19

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